1. Technical Field
The present disclosure relates to methods of forming semiconductor devices having one or more fin structures (“fins”), and to semiconductor devices having one or more fins. Some embodiments described in the present disclosure relate to finFETs having strained channels and/or to methods for fabricating finFETs having strained channels.
2. Discussion of the Related Art
Transistors are fundamental device elements of many modern digital processors and memory devices, and have found numerous applications in various areas of electronics including data processing, data storage, and high-power applications. Currently, there are a variety of transistor types and designs that may be used for different applications. Various transistor types include, for example, bipolar junction transistors (BJT), junction field-effect transistors (JFET), metal-oxide-semiconductor field-effect transistors (MOSFET), vertical channel or trench field-effect transistors, and superjunction or multi-drain transistors.
Two types of transistors which have emerged within the MOSFET family of transistors show promise for scaling to ultra-high density and nanometer-scale channel lengths. One of these transistor types is a so-called fin field-effect transistor or “finFET.” The channel of a finFET is formed in a three-dimensional fin that may extend from a surface of a substrate. FinFETs have favorable electrostatic properties for complimentary MOS (CMOS) scaling to smaller sizes. Because the fin is a three-dimensional structure, the transistor's channel can be formed on three or more surfaces of the fin, so that the finFET can exhibit a high current switching capability for a given surface area occupied on substrate. Since the channel and device can be raised from the substrate surface, there can be reduced electric field coupling between adjacent devices as compared to conventional planer MOSFETs.
The second type of transistor is called a fully-depleted, silicon-on-insulator or “FD-SOI” FET. The channel, source, and drain of an FD-SOI FET are formed in a thin planar semiconductor layer that overlies a thin insulator. Because the semiconductor layer and the underlying insulator are thin, the body of the transistor (which lies below the thin insulator) can act as a second gate. The thin layer of semiconductor on insulator permits higher body biasing voltages that can boost performance. The thin insulator also reduces leakage current to the transistor's body region relative to the leakage current that would otherwise occur in bulk FET devices.
FET performance may be improved by adjusting the strain in the FET's channel to increase carrier mobility within the channel. For silicon FETs, device performance may be improved by applying compressive strain to a p-channel device, and/or by applying tensile strain to an n-channel device. In some cases, channel strain may be induced by straining the FET's source and/or drain regions, such that the strain is transferred through the source and/or drain regions to the channel.